Freescale-semiconductor DSP56366 User Manual download pdf (Page 248)

Timer Modes of Operation

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

11-18 Freescale Semiconductor

clock signal can be taken from either the DSP56366 clock divided by two (CLK/2) or from the prescaler

clock output. Each subsequent clock signal increments the counter.

At the first appropriate transition of the external clock detected on the TIO0 signal, the TCF bit in the

TCSR is set and, if the TCIE bit is set, a compare interrupt is generated. The counter halts. The contents

of the counter are loaded into the TCR. The value of the TCR represents the delay between the setting of

the TE bit and the detection of the first clock edge signal on the TIO0 signal.

If the INV bit is set, a high-to-low transition signals the end of the timing period. If INV is cleared, a

low-to-high transition signals the end of the timing period.

If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated.

The counter contents can be read at any time by reading the TCR.

11.4.3 Pulse Width Modulation (PWM, Mode 7)

In this mode, the timer generates periodic pulses of a preset width. This function is available only on

timer 0.

Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the

TPCR. When first timer clock is received from either the DSP56366 internal clock divided by two (CLK/2)

or the prescaler clock output, the counter is loaded with the TLR value. Each subsequent timer clock

increments the counter.

When the counter equals the value in the TCPR, the TIO0 output pin is toggled and the TCF bit in the

TCSR is set. The contents of the counter are placed into the TCR. If the TCIE bit is set, a compare interrupt

is generated. The counter continues to be incremented on each timer clock.

If counter overflow has occurred, the TIO0 output pin is toggled, the TOF bit in TCSR is set, and an

overflow interrupt is generated if the TOIE bit is set. If the TRM bit is set, the counter is loaded with the

TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter

continues to be incremented on each timer clock.

This process is repeated until the timer is disabled by clearing the TE bit.

TIO0 signal polarity is determined by the value of the INV bit. When the counter is started by setting the

TE bit, the TIO0 signal assumes the value of the INV bit. On each subsequent toggling of the TIO0 signal,

the polarity of the TIO0 signal is reversed. For example, if the INV bit is set, the TIO0 signal generates the

following signal: 1010. If the INV bit is cleared, the TIO0 signal generates the following signal: 0101.

The counter contents can be read at any time by reading the TCR.

The value of the TLR determines the output period ($FFFFFF − TLR + 1). The timer counter increments

the initial TLR value and toggles the TIO0 signal when the counter value exceeds $FFFFFF.

Bit Settings Mode Characteristics

TC3 TC2 TC1 TC0 Mode Name Kind TIO0 Clock

0111 7Pulse Width ModulationPWMOutputInternal

1 2 ... 243 244 245 246 247 248 249 250 251 252 253 ... 365 366

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Freescale-semiconductor DSP56366 User Manual Page 248