Freescale-semiconductor DSP56366 User Manual download pdf (Page 237)

Timer/Event Counter Programming Model

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

Freescale Semiconductor 11-7

Clearing the TE bit disables the timer. The TE bit is cleared by the hardware RESET signal or the software

RESET instruction.

NOTE

When timer 0 is disabled and TIO0 is not in GPIO mode, the pin is tri-stated.

To prevent undesired spikes on TIO0 when Timer 0 is switched from

tri-state to an active state, TIO0 should be tied to the power supply with a

pullup or pulldown resistor.

11.3.4.2 TCSR Timer Overflow Interrupt Enable (TOIE) Bit 1

The TOIE bit is used to enable the timer overflow interrupts. Setting TOIE enables overflow interrupt

generation. The timer counter can hold a maximum value of $FFFFFF. When the counter value is at the

maximum value and a new event causes the counter to be incremented to $000000, the timer generates an

overflow interrupt.

Clearing the TOIE bit disables overflow interrupt generation. The TOIE bit is cleared by the hardware

RESET signal or the software RESET instruction.

11.3.4.3 TCSR Timer Compare Interrupt Enable (TCIE) Bit 2

The Timer Compare Interrupt Enable (TCIE) bit is used to enable or disable the timer compare interrupts.

Setting TCIE enables the compare interrupts. In the timer, PWM, or watchdog modes, a compare interrupt

is generated after the counter value matches the value of the TCPR. The counter will start counting up from

the number loaded from the TLR and if the TCPR value is N, an interrupt occurs after (N – M + 1) events,

where M is the value of TLR.

Clearing the TCIE bit disables the compare interrupts. The TCIE bit is cleared by the hardware RESET

signal or the software RESET instruction.

11.3.4.4 TCSR Timer Control (TC[3:0]) Bits 4–7

The four TC bits control the source of the timer clock, the behavior of the TIO0 signal, and the timer mode

of operation. Table 11-2 summarizes the TC bit functionality. A detailed description of the timer operating

modes is given in Section 11.4, "Timer Modes of Operation".

The TC bits are cleared by the hardware RESET signal or the software RESET instruction.

NOTE

If the clock is external, the counter is incremented by the transitions on the

TIO0 signal. The external clock is internally synchronized to the internal

clock, and its frequency should be lower than the internal operating

frequency divided by 4 (CLK/4).

To ensure proper operation, the TC[3:0] bits should be changed only when

the timer is disabled (when the TE bit in the TCSR has been cleared).

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Freescale-semiconductor DSP56366 User Manual Page 237