Freescale-semiconductor DSP56366 User Manual download pdf (Page 38)

Clock and PLL

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

2-4 Freescale Semiconductor

2.4 Clock and PLL

GND

(4) Address Bus Ground — GND

is an isolated ground for sections of the address bus I/O drivers. This

connection must be tied externally to all other chip ground connections. The user must provide

adequate external decoupling capacitors. There are four GND

connections.

GND

(4) Data Bus Ground — GND

is an isolated ground for sections of the data bus I/O drivers. This

connection must be tied externally to all other chip ground connections. The user must provide

adequate external decoupling capacitors. There are four GND

connections.

GND

(2) Bus Control Ground — GND

is an isolated ground for the bus control I/O drivers. This connection

must be tied externally to all other chip ground connections. The user must provide adequate external

decoupling capacitors. There are two GND

connections.

GND

Host Ground — GND

is an isolated ground for the HD08 I/O drivers. This connection must be tied

externally to all other chip ground connections. The user must provide adequate external decoupling

capacitors. There is one GND

connection.

GND

(2) SHI, ESAI, ESAI_1, DAX and Timer Ground — GND

is an isolated ground for the SHI, ESAI, ESAI_1,

DAX and Timer. This connection must be tied externally to all other chip ground connections. The user

must provide adequate external decoupling capacitors. There are two GND

connections.

Table 2-4 Clock and PLL Signals

Signal

Name

Type

State during

Reset

Signal Description

EXTAL Input Input External Clock Input — An external clock source must be connected to EXTAL

in order to supply the clock to the internal clock generator and PLL.

This input cannot tolerate 5 V.

PCAP Input Input PLL Capacitor — PCAP is an input connecting an off-chip capacitor to the PLL

filter. Connect one capacitor terminal to PCAP and the other terminal to V

CCP

If the PLL is not used, PCAP may be tied to V

, GND, or left floating.

PINIT/NMI

Input Input PLL Initial/Nonmaskable Interrupt — During assertion of RESET, the value of

PINIT/NMI

is written into the PLL Enable (PEN) bit of the PLL control register,

determining whether the PLL is enabled or disabled. After RESET

de assertion

and during normal instruction processing, the PINIT/NMI

Schmitt-trigger input

is a negative-edge-triggered nonmaskable interrupt (NMI) request internally

synchronized to internal system clock.

This input cannot tolerate 5 V.

Table 2-3 Grounds (continued)

Ground Name Description

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 365 366

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Freescale-semiconductor DSP56366 User Manual Page 38

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