Freescale-semiconductor DSP56366 User Manual download pdf (Page 108)

HDI08 – DSP-Side Programmer’s Model

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

6-14 Freescale Semiconductor

6.5.6.9 HPCR Host Request Open Drain (HROD) Bit 8

The HROD bit controls the output drive of the host request signals. In the single host request mode

(HDRQ=0 in ICR), if HROD is cleared and host requests are enabled (HREN=1 and HEN=1 in HPCR),

the HOREQ signal is always driven. If HROD is set and host requests are enabled, the HOREQ signal is

an open drain output.

In the double host request mode (HDRQ=1 in the ICR), if HROD is cleared and host requests are enabled

(HREN=1 and HEN=1 in the HPCR), the HTRQ and HRRQ signals are always driven. If HROD is set and

host requests are enabled, the HTRQ and HRRQ signals are open drain outputs.

6.5.6.10 HPCR Host Data Strobe Polarity (HDSP) Bit 9

If the HDSP bit is cleared, the data strobe signals are configured as active low inputs, and data is

transferred when the data strobe is low. If HDSP is set, the data strobe signals are configured as active high

inputs, and data is transferred when the data strobe is high. The data strobe signals are either HDS by itself

or HRD and HWR together.

6.5.6.11 HPCR Host Address Strobe Polarity (HASP) Bit 10

If the HASP bit is cleared, the address strobe (HAS) signal is an active low input, and the address on the

host address/data bus is sampled when the HAS signal is low. If HASP is set, HAS is an active high address

strobe input, and the address on the host address/data bus 8 is sampled when the HAS signal is high.

6.5.6.12 HPCR Host Multiplexed bus (HMUX) Bit 11

If the HMUX bit is set, the HDI08 latches the lower portion of a multiplexed address/data bus. In this mode

the internal address line values of the host registers are taken from the internal latch. If HMUX is cleared,

it indicates that the HDI08 is connected to a non-multiplexed type of bus, and the address lines are taken

from the HDI08 input signals.

6.5.6.13 HPCR Host Dual Data Strobe (HDDS) Bit 12

If the HDDS bit is cleared, the HDI08 operates in the single strobe bus mode. In this mode, the bus has a

single data strobe signal for both reads and writes. If HDDS is set, the HDI08 operates in the dual strobe

bus mode. In this mode, the bus has two separate data strobes, one for data reads, the other for data writes.

See Figure 6-7 and Figure 6-8 for more information on the two types of buses.

Figure 6-7 Single strobe bus

HRW

HDS

In the single strobe bus mode, the HDS (Data-Strobe) signal qualifies the access, while the

HRW (Read/Write) signal specifies the direction of the access.

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Freescale-semiconductor DSP56366 User Manual Page 108