Freescale-semiconductor DSP56366 User Manual download pdf (Page 123)

Servicing The Host Interface

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

Freescale Semiconductor 6-29

Figure 6-16 HDI08 Host Request Structure

6.7.3 Servicing Interrupts

If either the HOREQ/HTRQ or the HRRQ signal or both are connected to the host processor interrupt

inputs, the HDI08 can request service from the host processor by asserting one of these signals. The

HOREQ/HTRQ and/or the HRRQ signal is asserted when TXDE=1 and/or RXDF=1 and the

corresponding enable bit (TREQ or RREQ, respectively) is set. This is depicted in Figure 6-16.

HOREQ/HTRQ and HRRQ are normally connected to the host processor maskable interrupt inputs. The

host processor acknowledges host interrupts by executing an interrupt service routine. The host processor

can test RXDF and TXDE to determine the interrupt source. The host processor interrupt service routine

must read or write the appropriate HDI08 data register to clear the interrupt. HOREQ/HTRQ and/or HRRQ

is deasserted under the following conditions:

• The enabled request is cleared or masked

• The DSP is reset.

If the host processor is a member of the MC68000 family, there is no need for the additional step when the

host processor reads the ISR to determine how to respond to an interrupt generated by the DSP. Instead,

the DSP automatically sources the contents of the IVR on the data bus when the host processor

acknowledges the interrupt by asserting HACK. The contents of the IVR are placed on the host data bus

while HOREQ and HACK are simultaneously asserted. The IVR data tells the MC680XX host processor

which interrupt routine to execute to service the DSP.

HREQ 0 0 HF3 HF2 TRDY TXDE RXDF

STATUS

ISR

INIT 0 HLEND HF1 HF0 HDRQ TREQ RREQ

ICR

ENABLE

Host Request

ASSERTED

HOREQ

HRRQ

HTRQ

1 2 ... 118 119 120 121 122 123 124 125 126 127 128 ... 365 366

No comments

Freescale-semiconductor DSP56366 User Manual Page 123