Freescale-semiconductor DSP56366 User Manual download pdf (Page 243)

Timer Modes of Operation

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

Freescale Semiconductor 11-13

— Event counter, mode 3: Internal timer interrupt generated by an external clock

•Measurement

— Input width, mode 4: Input pulse width measurement

— Input pulse, mode 5: Input signal period measurement

— Capture, mode 6: Capture external signal

• PWM, mode 7: Pulse Width Modulation

• Watchdog

— Pulse, mode 9: Output pulse, internal clock

— Toggle, mode 10: Output toggle, internal clock

These modes are described in detail below. Timer modes are selected by setting the TC[3:0] bits in the

TCSR. Table 11-2 and Table 11-3 show how the different timer modes are selected by setting the bits in

the TCSR. Table 11-2 also shows the TIO0 signal direction and the clock source for each timer mode.

NOTE

To ensure proper operation, the TC[3:0] bits should be changed only when

the timer is disabled (i.e., when the TE bit in the TCSR is cleared).

11.4.1 Timer Modes

11.4.1.1 Timer GPIO (Mode 0)

In this mode, the timer generates an internal interrupt when a counter value is reached (if the timer compare

interrupt is enabled). Note that any of the three timers can be placed in GPIO mode to generate internal

interrupts, but only timer 0 provides actual external GPIO access on the TIO0 signal.

Set the TE bit to clear the counter and enable the timer. Load the value the timer is to count into the TCPR.

The counter is loaded with the TLR value when the first timer clock signal is received. The timer clock

can be taken from either the DSP56366 clock divided by two (CLK/2) or from the prescaler clock output.

Each subsequent clock signal increments the counter.

When the counter equals the TCPR value, the TCF bit in TCSR is set, and a compare interrupt is generated

if the TCIE bit is set. If the TRM bit in the TCSR is set, the counter is reloaded with the TLR value at the

next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be

incremented on each timer clock signal.

This process is repeated until the timer is disabled (i.e., TE is cleared).

If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated.

The counter contents can be read at any time by reading the TCR.

Bit Settings Mode Characteristics

TC3 TC2 TC1 TC0 TIO0 Clock # KIND NAME

0000GPIOInternal0 Timer GPIO

1 2 ... 238 239 240 241 242 243 244 245 246 247 248 ... 365 366

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Freescale-semiconductor DSP56366 User Manual Page 243