Freescale-semiconductor DSP56366 User Manual download pdf (Page 174)

ESAI Programming Model

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

8-24 Freescale Semiconductor

8.3.3.5 RCCR Receiver Clock Polarity (RCKP) - Bit 18

The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked

out and latched in. If RCKP is cleared the data and the frame sync are clocked out on the rising edge of the

receive bit clock and the frame sync is latched in on the falling edge of the receive bit clock. If RCKP is

set the falling edge of the receive clock is used to clock the data and frame sync out and the rising edge of

the receive clock is used to latch the frame sync in.

8.3.3.6 RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19

The Receiver Frame Sync Polarity (RFSP) determines the polarity of the receive frame sync signal. When

RFSP is cleared the frame sync signal polarity is positive (i.e the frame start is indicated by a high level

on the frame sync pin). When RFSP is set the frame sync signal polarity is negative (i.e the frame start is

indicated by a low level on the frame sync pin).

8.3.3.7 RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20

The Receiver High Frequency Clock Polarity (RHCKP) bit controls on which bit clock edge data and

frame sync are clocked out and latched in. If RHCKP is cleared the data and the frame sync are clocked

out on the rising edge of the receive bit clock and the frame sync is latched in on the falling edge of the

receive bit clock. If RHCKP is set the falling edge of the receive clock is used to clock the data and frame

sync out and the rising edge of the receive clock is used to latch the frame sync in.

8.3.3.8 RCCR Receiver Clock Source Direction (RCKD) - Bit 21

The Receiver Clock Source Direction (RCKD) bit selects the source of the clock signal used to clock the

receive shift register in the asynchronous mode (SYN=0) and the IF0/OF0 flag direction in the

synchronous mode (SYN=1).

In the asynchronous mode when RCKD is set, the internal clock source becomes the bit clock for the

receive shift registers and word length divider, and is the output on the SCKR pin. In the asynchronous

mode when RCKD is cleared, the clock source is external; the internal clock generator is disconnected

from the SCKR pin, and an external clock source may drive this pin.

Table 8-6 Receiver High Frequency Clock Divider

RFP3-RFP0 Divide Ratio

$0 1

$1 2

$2 3

$3 4

... ...

$F 16

1 2 ... 169 170 171 172 173 174 175 176 177 178 179 ... 365 366

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Freescale-semiconductor DSP56366 User Manual Page 174