Freescale-semiconductor DSP56366 User Manual download pdf (Page 113)

HDI08 – External Host Programmer’s Model

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

Freescale Semiconductor 6-19

One of the most innovative features of the host interface is the host command feature. With this feature,

the host processor can issue vectored interrupt requests to the DSP core. The host may select any of 128

DSP interrupt routines to be executed by writing a vector address register in the HDI08. This flexibility

allows the host programmer to execute up to 128 pre-programmed functions inside the DSP. For example,

host interrupts can allow the host processor to read or write DSP registers (X, Y, or program memory

locations), force interrupt handlers (e.g. IRQA, IRQB, etc. interrupt routines), and perform control and

debugging operations if interrupt routines are implemented in the DSP to perform these tasks.

6.6.1 Interface Control Register (ICR)

The ICR is an 8-bit read/write control register used by the host processor to control the HDI08 interrupts

and flags. The ICR cannot be accessed by the DSP core. The ICR is a read/write register, which allows the

use of bit manipulation instructions on control register bits. The control bits are described in the following

paragraphs.

Bits 2, 5 and 6 of the ICR are affected by the condition of HDM[2:0] (HCR bits 5-7), as shown in

Figure 6-12.

Table 6-8 HDI08 Host Side Register Map

Host

Address

Big Endian

HLEND=0

Little Endian

HLEND=1

Function

0 ICR ICR Interface Control

1 CVR CVR Command Vector

2 ISR ISR Interface Status

3 IVR IVR Interrupt Vector

4 00000000 00000000 Unused

5 RXH/TXH

The RXH/TXH register is always mapped to the most significant byte of the DSP word.

RXL/TXL

Receive/Transmit

Bytes

6 RXM/TXM RXM/TXM

7 RXL/TXL RXH/TXH

Host Data Bus

H0 - H7

Host Data Bus

H0 - H7

1 2 ... 108 109 110 111 112 113 114 115 116 117 118 ... 365 366

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Freescale-semiconductor DSP56366 User Manual Page 113