Freescale Semiconductor EETX4K User Manual download pdf (Page 41)

Block Guide — S12EETX4KV0 V00.04

BDM status register. This BDM action will cause the MCU to override the Flash security state and the

MCU will be unsecured. Once the MCU is unsecured, BDM commands will be enabled and the Flash

security byte may be programmed to the unsecure state.

4.6 Resets

4.6.1 EEPROM Reset Sequence

On each reset, the EEPROM module executes a reset sequence to hold CPU activity while loading the

EPROT register from the EEPROM memory according to Table 3-1.

4.6.2 Reset While EEPROM Command Active

If a reset occurs while any EEPROM command is in progress, that command will be immediately aborted.

The state of a word being programmed or the sector / block being erased is not guaranteed.

4.7 Interrupts

The EEPROM module can generate an interrupt when all EEPROM command operations have completed,

when the EEPROM address, data and command buffers are empty.

Vector addresses and their relative interrupt priority are determined at the MCU level.

4.7.1 Description of EEPROM Interrupt Operation

The logic used for generating interrupts is shown in Figure 4-8.

The EEPROM module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable

bits to generate the EEPROM command interrupt request.

Table 4-2 EEPROM Interrupt Sources

Interrupt Source Interrupt Flag Local Enable

Global (CCR)

Mask

EEPROM Address, Data and

Command Buffers empty

CBEIF

(ESTAT register)

CBEIE

(ECNFG register)

I-Bit

All EEPROM commands completed

CCIF

(ESTAT register)

CCIE

(ECNFG register)

I-Bit

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Freescale Semiconductor EETX4K User Manual Page 41